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A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current
Conference paper
Authors:
Mao, Jiaji
;
Guo, Mingqiang
;
Sin, Sai-Weng
;
Martins, Rui Paulo
Favorite
|
View/Download:35/0
|
TC[WOS]:
2
TC[Scopus]:
3
|
Submit date:2018/10/30
Analog-to-digital conversion
digital background calibration
pipelined ADC
split ADC
opamp-sharing technique
A 14-Bit Split-Pipeline ADC with Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current
Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 10,Page: 1380-1384
Authors:
Mao J.
;
Guo M.
;
Sin S.-W.
;
Martins R.P.
Favorite
|
View/Download:8/0
|
TC[WOS]:
2
TC[Scopus]:
3
|
Submit date:2019/02/11
Analog-to-digital conversion
digital background calibration
opamp-sharing technique
pipelined ADC
split ADC
A 0.4 v 6.4 μw 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °c for Wearable and Sensing Applications
Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:
Lei K.-M.
;
Mak P.-I.
;
Martins R.P.
Favorite
|
View/Download:24/0
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2019/02/11
bootstrap
bulk-driven amplifier
CMOS
relaxation oscillator (RxO)
ultra-low-voltage (ULV)
wearable devices
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:
Chan, Chi-Hang
;
Zhu, Yan
;
Zhang, Wai-Hong
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:55/0
|
TC[WOS]:
11
TC[Scopus]:
15
|
Submit date:2018/10/30
1-then-2 B/cycle Sar Adc
Analog-to-digital Conversion
Background Offset Calibration
Multi-bit/cycle Sar Adc
Time Interleaving
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:
Qiu, Lei
;
Tang, Kai
;
Zheng, Yuanjin
;
Siek, Liter
;
Zhu, Yan
;
U, Seng-Pan
Favorite
|
View/Download:40/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2018/10/30
Digital Background Calibration
Subradix-2
Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)
Time Interleaved (Ti)
Time Skew
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:
Chan, Chi-Hang
;
Zhu, Yan
;
Li, Cheng
;
Zhang, Wai-Hong
;
Ho, Iok-Meng
;
Wei, Lai
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:36/0
|
TC[WOS]:
12
TC[Scopus]:
19
|
Submit date:2018/10/30
Reference Buffer
Reference Error Calibration
Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)
Threshold Reconfigurable Comparator
Split-based time-interleaved ADC with digital background timing-skew calibration
Conference paper
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, Italy, JUN 12-15, 2017
Authors:
Guo M.
;
Sin S.-W.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:20/0
|
TC[WOS]:
1
TC[Scopus]:
1
|
Submit date:2019/02/11
Adc
Converters
Digital Background Calibration
Split-adc
Time-interleaving
Timing
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration
Conference paper
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Toyama, JAPAN, NOV 07-09, 2016
Authors:
Qiu L.
;
Kai T.
;
Zhu Y.
;
Siek L.
;
Zheng Y.
;
Seng-Pan U.
Favorite
|
View/Download:16/0
|
TC[WOS]:
8
TC[Scopus]:
9
|
Submit date:2019/02/14
Sar Adcs
Time Skew Calibration
Time-interleaved
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 7,Page: 2603-2607
Authors:
Jianwei Liu
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo da Silva Martins
Favorite
|
View/Download:30/0
|
TC[WOS]:
7
TC[Scopus]:
9
|
Submit date:2019/02/14
Background Linearity Calibration
Splitdigital- To-analog Converter (Dac)
Successive Approximation Register (Sar) Adc
Uniform Quantization Theory (Uqt)
A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration
Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, Singapore, 11-13 Nov. 2013
Authors:
Li Ding
;
Wenlan Wu
;
Sai-Weng Sin
;
Seng-Pan U
;
R.P.Martins
Favorite
|
View/Download:17/0
|
TC[WOS]:
3
TC[Scopus]:
3
|
Submit date:2019/02/11