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A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018
Authors:  Iat-Fai Sun;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:4/0  |  Submit date:2019/03/12
8-phase Ring Voltage-controlled Oscillators (Rvco)  Cmos  Feedforward Coupling (Fc)  Phase Noise  Bimodal Oscillation  Clock Generation  Lo Generation  
Temporal establishment of neural cell identity in vivo and in vitro Journal article
JOURNAL OF TISSUE ENGINEERING AND REGENERATIVE MEDICINE, 2017,Volume: 11,Issue: 9,Page: 2582-2589
Authors:  Yuen, Shun Ming;  Kwok, Hang Fai
Favorite  |  View/Download:8/0  |  Submit date:2018/10/30
Temporal Regulation  Neural Stem Cells  Embryonic Stem Cells  Induced Pluripotent Stem Cells  Cis-regulatory Elements  Cell Fates  Neural Specification  
Solving large complex problems using a higher order basis: Parallel out-of-core integral equation solvers involving a million unknowns Conference paper
2014 IEEE International Wireless Symposium, IWS 2014
Authors:  Sarkar T.K.;  Zhang Y.;  Donoro D.G.;  Moon H.;  Salazar-Palma M.;  Ting S.W.
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Computational electromagnetics  Method of Moments  Million unknowns  Out-of-core solver  parallel computation  
Systematic analysis and cancellation of kickback noise in a dynamic latched comparator Journal article
Analog Integrated Circuits and Signal Processing, 2013,Volume: 77,Issue: 2,Page: 277-284
Authors:  Ka-Meng Lei;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Cmos  Dynamic Latched Comparator  Kickback Noise  
An Open-Loop Multi-Phase Local-Oscillator Generation Technique Book chapter
出自: Low Power Emerging Wireless Technologies:CRC Press, 2013, 页码: 233-248
Authors:  Kai-Fai Un;  Pui-In Mak;  Rui P. Martins
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Cyber security and privacy issues in smart grids Journal article
IEEE Communications Surveys and Tutorials, 2012,Volume: 14,Issue: 4,Page: 981
Authors:  Liu J.;  Xiao Y.;  Li S.;  Liang W.;  Chen C.L.P.
View  |  Adobe PDF(1244Kb)  |  Favorite  |  View/Download:238/6  |  Submit date:2018/10/30
Accountability  Ami  Privacy  Scada  Security  Smart Grid  
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Kuala Lumpur, MALAYSIA, DEC 06-09, 2010
Authors:  Jiang Y.;  Wong K.-F.;  Cai C.-Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
Clock-jitter Sensitivity  Continuous-time  Sigma-delta Modulator  Switched Current Dac  
A process-insensitive current-controlled delay generator with threshold voltage compensation Conference paper
2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 8-10 Nov. 2010
Authors:  Wei H.-G.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
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Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-toDigital Conversion Systems Conference paper
Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004, University of Macau, Macao, China, Oct 2004
Authors:  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:3/0  |  Submit date:2019/03/29