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A 13-bit 8-kS/s δ ∑ Readout IC Using ZCB Integrators with an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 4,Page: 843-853
Authors:  Li,Bing;  Na,Ji Ping;  Wang,Wei;  Liu,Jia;  Yang,Qian;  Mak,Pui In
Favorite  |  View/Download:2/0  |  Submit date:2019/08/22
CMOS  figure of merit (FoM)  oversampling Δ-Σ modulation  power-supply rejection ratio (PSRR)  readout IC (ROIC)  resistive sensor  Wheatstone bridge  zero-crossing-based (ZCB) integrator  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:10/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Page: 1 - 12
Authors:  Shiheng Yang;  Jun Yin;  Haidong Yi;  Wei-Han Yu;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/03/12
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)  
A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019,Volume: 66,Issue: 1,Page: 116-120
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite  |  View/Download:7/0  |  Submit date:2019/01/17
I/O buffer  mixed-voltage tolerant  PVT variation  leakage  slew rate compensation  
A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA Journal article
Integration, 2019
Authors:  Balan Z.;  Ramiah H.;  Rajendran J.;  Vitee N.;  Shasidharan P.N.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:1/0  |  Submit date:2019/02/11
Bluetooth Low Energy (BLE)  CMOS receiver  Current-reuse  Forward body bias  I/Q mixers  Low power  Quadrature LNA  Voltage-controlled oscillator (VCO)  ZigBee  
Many-objective sizing optimization of a class-C/D VCO for ultralow-power iot and ultralow-phase-noise cellular applications Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 1,Page: 69-82
Authors:  Martins R.;  Lourenco N.;  Horta N.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
Dual-mode Voltage-controlled Oscillator (Voc)  Electronic Design Automation (Eda)  Many-objective Optimization  Multitest Bench Sizing Optimization  Radio Frequency (Rf) Integrated Circuits (Ics)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 237-241
Authors:  Lim C.C.;  Ramiah H.;  Yin J.;  Kumar N.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/14
Class-c  Cmos  Current-reuse  Mode Switching  Phase Noise (Pn)  Single-ended Complementary (Sec)  Voltage-controlled Oscillator (Vco)  Wideband