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A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite  |  View/Download:30/0  |  Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end Conference paper
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
Authors:  Chan C.-H.;  Zhu Y.;  Zheng Z.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
A 0.4 v 6.4 μw 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °c for Wearable and Sensing Applications Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:  Lei K.-M.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:15/0  |  Submit date:2019/02/11
bootstrap  bulk-driven amplifier  CMOS  relaxation oscillator (RxO)  ultra-low-voltage (ULV)  wearable devices  
A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 2,Page: 146-150
Authors:  Yi H.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Bootstrapped  Charge Pump (Cp)  Cmos  Energy Harvesting  Reverse Current  Ring-vco  Ultra-low Voltage  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration