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Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:10/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite  |  View/Download:13/0  |  Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW Conference paper
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, PEOPLES R CHINA, MAY 19-23, 2013
Authors:  Yun Du;  Tao He;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, DEC 02-05, 2012
Authors:  Yun Du;  Tao He;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
Statistical spectra and distortion analysis of time-interleaved sampling bandwidth mismatch Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2008,Volume: 55,Issue: 7,Page: 648-652
Authors:  Sai-Weng Sin;  U.-Fat Chio;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Bandwidth Mismatches  Sampled-data Systems  Time-interleaved (Ti) Analog-to-digital Converter (Adc)  
Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering Book
US:Springer US, 2006
Authors:  U Seng Pan;  Martins Rui Paulo;  Epifanio da Franca Jose de Albuquerque
Favorite  |  View/Download:7/0  |  Submit date:2019/02/26
Cmos  Cmos Analog Integrated Circuit  Filter  Front-end Filtering  Gain & Offset Compensation  High-frequency  Multirate Signal Processing  Secs  Switched-capacitor  The Kluwer International Series In engIneerIng And Computer  Timing-mismatch And Jitter  Calculus  Consumption  Integrated Circuit  
Improved switched-capacitor interpolators with reduced sample-and-hold effects Journal article
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000,Volume: 47,Issue: 8,Page: 665-684
Authors:  Seng-Pan U.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11