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A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | View/Download:50/0 | TC[WOS]:11 TC[Scopus]:0 | Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:20/0 | TC[WOS]:18 TC[Scopus]:0 | Submit date:2018/11/06
A background amplifier offset calibration technique for high-resolution pipelined ADCs Conference paper
Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010, Montreal, QC, Canada, 20-23 June 2010
Authors:  Ding L.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite | View/Download:8/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11