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A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | View/Download:70/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2020/12/04
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CT-DSM)  preliminary sampling and quantization (PSQ) technique  single amplifier biquad (SAB)  successiveapproximation-register (SAR) architecture-based quantizer (QTZ)  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | View/Download:33/0 | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 1,Page: 82-93
Authors:  Li C.;  Chan C.-H.;  Zhu Y.;  Martins R.P.
Favorite | View/Download:17/0 | TC[WOS]:1 TC[Scopus]:3 | Submit date:2019/02/11
analog-to-digital converter (ADC)  reference buffer  Reference error  reference ripple  successive-approximation-register (SAR)  
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019,Volume: 66,Issue: 1,Page: 82-93
Authors:  Li, Cheng;  Chan, Chi-Hang;  Zhu, Yan;  Martins, Rui P.
Favorite | View/Download:22/0 | TC[WOS]:1 TC[Scopus]:3 | Submit date:2019/01/17
Reference error  reference buffer  successive-approximation-register (SAR)  analog-to-digital converter (ADC)  reference ripple  
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538
Authors:  Wang, X. Shawn;  Jin, Xin;  Du, Jieqiong;  Li, Yilei;  Du, Yuan;  Wong, Chien-Heng;  Kuan, Yen-Cheng;  Chan, Chi-Hang;  Chang, Mau-Chung Frank
Favorite | View/Download:10/0 | TC[WOS]:3 TC[Scopus]:3 | Submit date:2019/01/17
Analog-to-digital converter (ADC)  virtual-ground sampling  SAR  time-interleaved  
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 11,Page: 2279-2289
Authors:  Wang, Guan Cheng;  Zhu, Yan;  Chan, Chi-Hang;  Seng-Pan, U.;  Martins, Rui P.
Favorite | View/Download:19/0 | TC[WOS]:0 TC[Scopus]:1 | Submit date:2019/01/17
Bridge digital-to-analog converter (DAC)  gain error calibration  successive approximation register (SAR)  analog-to-digital converters (ADCs)  testing signal generation (TSG)  
A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE SENSORS JOURNAL, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny, Sharma;  Chen, Yong;  Boon, Chirn Chye
Favorite | View/Download:20/0 | TC[WOS]:1 TC[Scopus]:4 | Submit date:2018/10/30
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register  
A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE Sensors Journal, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny S.;  Chen Y.;  Boon C.C.
Favorite | View/Download:6/0 | TC[WOS]:1 TC[Scopus]:4 | Submit date:2019/02/14
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register  
Quick and cost-efficient A/D converter static characterization using low-precision testing signal Journal article
MICROELECTRONICS JOURNAL, 2018,Volume: 74,Page: 86-93
Authors:  Qin, Wei Wei;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | View/Download:31/0 | TC[WOS]:0 TC[Scopus]:1 | Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Static Characterization Estimation  Adc Testing  Ramp Testing  Nonlinear Input Signal  Attenuated Input Signal  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite | View/Download:40/0 | TC[WOS]:3 TC[Scopus]:5 | Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew