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A 5-bit 2 GS/s binary-search ADC with charge-steering comparators Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, NOV 06-08, 2017
Authors:  Chio, U-Fat;  Sin S.-W.;  Seng-Pan U.;  Maloberti F.;  Martins R.P.
Favorite | View/Download:21/0 | TC[WOS]:0 TC[Scopus]:1 | Submit date:2019/02/11
Binary-search Adc  Asynchronous  Charge-steering  
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2013,Volume: 48,Issue: 8,Page: 1783-1794
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:20/0 | TC[WOS]:22 TC[Scopus]:30 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc  
Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters Journal article
Analog Integrated Circuits and Signal Processing, 2013,Volume: 76,Issue: 1,Page: 35-46
Authors:  Chen-Yan Cai;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite | View/Download:9/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
Ct Δς Modulator  Excess-loop-delay Compensation Techniques For Hybrid Active-passive Loop-filter  Excess-loop-delay For Hybrid Active-passive Loop-filter  Hybrid Active-passive Loop-filter  
Delay generator Patent
专利类型: 发明专利, 专利号: US8441295B2, 申请日期: 2011-11-04, 公开日期: 2013-05-14
Authors:  He-Gong Wei;  U-Fat CHIO;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite | View/Download:26/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/26
延迟产生器 Patent
专利类型: 发明专利, 专利号: TW201246793A, 申请日期: 2011-05-09, 公开日期: 2012-11-16
Authors:  Wei HG(魏和功);  Zhao RF(赵汝法);  Xian SR(冼世荣);  余成斌 U;  马 许愿
Favorite | View/Download:21/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/04/18
An ELD tracking compensation technique for active-RC CT ΣΔ modulators Conference paper
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, USA, AUG 05-08, 2012
Authors:  Chen-Yan Cai;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui. P. Martins
Favorite | View/Download:14/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC Conference paper
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, USA, 9-12 Sept. 2012
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | View/Download:18/0 | TC[WOS]:1 TC[Scopus]:7 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Time-interleaved  Sar Adc  Two-step Adc  
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS Conference paper
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, Jeju, South Korea, 14-16 Nov. 2011
Authors:  Chan C.-H.;  Zhu Y.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | View/Download:20/0 | TC[WOS]:0 TC[Scopus]:57 | Submit date:2019/02/11
A passive excess-loop-delay compensation technique for Gm-C based continuous-time ΣΔ modulators Conference paper
Midwest Symposium on Circuits and Systems, Yonsei Univ, Seoul, SOUTH KOREA, AUG 07-10, 2011
Authors:  Cai C.-Y.;  Jiang Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite | View/Download:18/0 | TC[WOS]:0 TC[Scopus]:4 | Submit date:2019/02/11
A charge pump based timing-skew calibration for time-interleaved ADC Conference paper
Midwest Symposium on Circuits and Systems, Yonsei Univ, Seoul, SOUTH KOREA, AUG 07-10, 2011
Authors:  Zhang P.;  Chen Z.;  Wei H.-G.;  Sin S.-W.;  Seng-Pan U.;  Wang Z.;  Martins R.P.
Favorite | View/Download:15/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
Adc  Calibration  Charge Pump  Time-interleaved (Ti)  Timing Skew