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A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | View/Download:0/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2020/12/04
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CT-DSM)  preliminary sampling and quantization (PSQ) technique  single amplifier biquad (SAB)  successiveapproximation-register (SAR) architecture-based quantizer (QTZ)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite | View/Download:29/0 | TC[WOS]:3 TC[Scopus]:6 | Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 12,Page: 2979-2991
Authors:  Yin J.;  Mak P.-I.;  Maloberti F.;  Martins R.P.
Favorite | View/Download:17/0 | TC[WOS]:9 TC[Scopus]:14 | Submit date:2019/02/11
1/f3 Phase Noise Corner  Divided Output  Flicker Noise  Impulse Sensitivity Function (Isf)  Phase Combiner  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Supply Voltage  Time-interleaved (Ti).  
Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 3,Page: 712-723
Authors:  Cheng L.;  Ki W.-H.;  Lu Y.;  Yim T.-S.
Favorite | View/Download:13/0 | TC[WOS]:47 TC[Scopus]:54 | Submit date:2019/02/14
Active Rectifier  Comparator Delay  Delay Compensation  Inductive Coupling  Pvt Variations  Resonant Wireless Power Transfer (R-wpt)  Reverse Current Control  
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2013,Volume: 48,Issue: 8,Page: 1783-1794
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:20/0 | TC[WOS]:22 TC[Scopus]:30 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc