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A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 20-24 Feb. 2011
Authors:  Wei H.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.;  Maloberti F.
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A 0.024mm28b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Wei, Hegong;  Chan, Chi-Hang;  Chio, U.-Fat;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui;  Maloberti, Franco
Favorite  |  View/Download:1/0  |  Submit date:2018/11/06
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications Conference paper
2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, Athens, Greece, 12-15 Dec. 2010
Authors:  Yin G.;  Chio U.-F.;  Wei H.-G.;  Sin S.-W.;  U S.-P.;  Martins R.P.;  Wang Z.
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Bio-medical Applications  Pipelined  Sar Adc  Ultra-low Power  
Parasitics nonlinearity cancellation technique for split DAC architecture by using capacitive charge-pump Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs Conference paper
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 30 May-2 June 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
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Parasitic calibration by two-step ratio approaching techinque for split capacitor array SAR ADCs Conference paper
2009 International SoC Design Conference, ISOCC 2009, Busan, South Korea, 22-24 Nov. 2009
Authors:  Wong S.-S.;  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
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Analog-to-digital Converter (Adc)  Offset Calibration  Parasitic Calibration  Split Capacitor Array  Sucessive Approximation Register (Sar)  
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Macao, PEOPLES R CHINA, NOV 30-DEC 03, 2008
Authors:  Chio U.-F.;  Wei H.-G.;  Zhu Y.;  Sin S.-W.;  Seng-Pan U.;  RPMartins
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Linearity analysis on a series-split capacitor array for high-speed SAR ADCs Conference paper
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, Knoxville, TN, AUG 10-13, 2008
Authors:  Yan Zhu;  U-Fat Chio;  He-Gong Wei;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:18/0  |  Submit date:2019/02/11