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A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:24/0 | TC[WOS]:9 TC[Scopus]:11 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite | View/Download:29/0 | TC[WOS]:7 TC[Scopus]:7 | Submit date:2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration  
Analog to Digital Converter Circuit Patent
专利类型: 发明专利, 专利号: TWI446723B, 申请日期: 2011-03-08,
Authors:  Sin,S-W(冼世荣);  Ding L(丁立);  Zhu Y(诸嫣);  Wei HG(魏和功);  Chan CH(陈知行);  Chio UF(赵汝法);  U SP(余成斌);  Martins,R(马许愿);  Franco,M
Favorite | View/Download:26/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US8659461B1, 申请日期: 2012-11-13, 公开日期: 2014-02-25
Authors:  Yan Zhu;  Chi Hang Chan;  Sai Weng Sin;  Seng Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite | View/Download:22/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption Patent
专利类型: 发明专利, 专利号: US8427355B2, 申请日期: 2011-09-14,
Authors:  Sai-Weng Sin;  Li Ding;  Yan Zhu;  He-Gong Wei;  Chi-Hang Chan;  U-Fat Chio;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite | View/Download:18/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: TW201242261A, 申请日期: 2011-03-08, 公开日期: 2012-10-16
Authors:  Xian SR(冼世荣);  Ding L(丁立);  Zhu Y(诸嫣);  Wei HG(魏和功);  Chen ZX(陈知行);  Zhao RF(赵汝法);  余成斌 U;  Ma XY(马许愿);  马洛贝尔蒂 佛朗哥
Favorite | View/Download:23/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/04/18
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US20120229313A1, 申请日期: 2011-09-14, 公开日期: 2012-09-13
Authors:  Sai-Weng SIN;  He-Gong WEI;  Franco MALOBERTI;  Li DING;  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Seng-Pan U;  Rui Paulo da Silva MARTINS
Favorite | View/Download:15/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/26
Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite | View/Download:16/0 | TC[WOS]:5 TC[Scopus]:6 | Submit date:2019/02/11
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation Journal article
IEEE Journal of Solid-State Circuits, 2012,Volume: 47,Issue: 11,Page: 2614-2626
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite | View/Download:18/0 | TC[WOS]:21 TC[Scopus]:26 | Submit date:2018/10/30
Decoupled Flip-around Mdac  Offset-cancellation  Pipelined-sar Adc  Vdd -attenuator  
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation Conference paper
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, Jeju, SOUTH KOREA, NOV 14-16, 2011
Authors:  Zhu Y.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.;  Maloberti F.
Favorite | View/Download:29/0 | TC[WOS]:21 TC[Scopus]:18 | Submit date:2019/02/11