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An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Authors:  Wang X.S.;  Chan C.-H.;  Du J.;  Wong C.-H.;  Li Y.;  Du Y.;  Kuan Y.-C.;  Hu B.;  Chang M.-C.F.
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