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Research Outputs

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  Total Views
 81

  Access Source
    internal: 1
    External: 80
    Domestic: 32
    Abroad: 49

  Annual Views
 81

  Access Source
    internal: 1
    External: 80
    Domestic: 32
    Abroad: 49

  Monthly Views
 2

  Access Source
    internal: 0
    External: 2
    Domestic: 1
    Abroad: 1

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Visits

1. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS [33]
2. A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC [21]
3. Linearity analysis on a series-split capacitor array for high-spee.. [18]
4. Passive Noise Shaping in SAR ADC With Improved Efficiency [17]
5. Design and experimental verification of a power effective Flash-SA.. [17]
6. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With B.. [16]
7. A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipel.. [16]
8. 60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Referen.. [14]
9. Metastablility in SAR ADCs [14]
10. A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offs.. [13]
11. Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial .. [13]
12. A rapid power-switchable track-and-hold amplifier in 90-nm CMOS [12]
13. A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with sing.. [12]
14. A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC f.. [12]
15. A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined R.. [11]
16. A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset ca.. [11]
17. Parasitic calibration by two-step ratio approaching techinque for .. [11]
18. Uniform Quantization Theory-Based Linearity Calibration for Split .. [11]
19. A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC.. [10]
20. A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC [10]
21. Multi-merged-switched redundant capacitive DACs for 2b/cycle SAR A.. [10]
22. A voltage feedback charge compensation technique for split DAC arc.. [10]
23. A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS [9]
24. A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-inte.. [9]
25. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interl.. [9]
26. A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around .. [9]
27. Parasitics nonlinearity cancellation technique for split DAC archi.. [9]
28. A power scalable 6-bit 1.2GS/s flash ADC with power on/off track-a.. [9]
29. Analysis of common-mode interference and jitter of clock receiver .. [8]
30. A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-.. [8]
31. A 312 ps response-time LDO with enhanced super source follower in .. [8]
32. A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC [8]
33. An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC [8]
34. A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switc.. [8]
35. Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pi.. [8]
36. A reconfigurable low-noise dynamic comparator with offset calibrat.. [8]
37. On-chip small capacitor mismatches measurement technique using bet.. [8]
38. Split-SAR ADCs: Improved linearity with power and speed optimizati.. [7]
39. A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS [7]
40. A missing-code-detection gain error calibration achieving 63dB SNR.. [7]
41. A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC wi.. [7]
42. An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SA.. [7]
43. Thermal and Reference Noise Analysis of Time-Interleaving SAR and .. [7]
44. A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC st.. [7]
45. An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused .. [7]
46. A voltage-controlled capacitance offset calibration technique for .. [7]
47. A power-efficient capacitor structure for high-speed charge recycl.. [7]
48. Cascade Analog to Digital Converting System [7]
49. Histogram-based ratio mismatch calibration for bridge-DAC in 12-bi.. [6]
50. Design techniques for nanometer wideband power-efficient CMOS ADCs [6]
51. A Process- and temperature- insensitive current-controlled delay g.. [6]
52. A self-timing switch-driving register by precharge-evaluate logic .. [6]
53. A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter b.. [6]
54. A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm.. [5]
55. Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low .. [5]
56. Analog to Digital Converter Circuit [5]
57. N-Bits Successive Approximation Register Analog-to-Digital Convert.. [5]
58. Analog to digital converter circuit [5]
59. Analog to digital converter circuit [4]
60. N-bits successive approximation register analog-to-digital convert.. [3]
61. Analog to digital converter circuit [3]
62. Sampling front-end for analog to digital converter [3]
63. N-Bits Successive Approximation Register Analog-to-Digital Convert.. [2]
64. Comparator and Calibration Thereof [1]

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