UM
The hardware thread interface design and adaptation on dynamically reconfigurable SoC
Wang Y.; Chen W.-N.; Wang X.-W.; You H.-J.; Peng C.-L.
2009-10-12
Source PublicationProceedings - 2009 International Conference on Embedded Software and Systems, ICESS 2009
Pages173-178
AbstractNowadays, one of the challenges for creating a mixed hardware/software application on dynamically reconfigurable SoC is how to provide a unified programming model for hybrid hardware/software tasks and a portable interface adaptation for dynamically reconfigurable hardware tasks. In this paper, a POSIX-compliant hardware thread interface is proposed for data stream driven applications, serving for unified hardware/software multithread programming. At the same time, the stub/interface adaptation mechanism is also presented to support shared buffer based inter-thread communication/synchronization. At last, the experimental results on AES encryption/decryption hardware thread show that the interface design and adaptation could exploit programming transparency while effectively keep hardware efficiency.
KeywordHardware thread Interface adaptation Stub thread
DOI10.1109/ICESS.2009.56
URLView the original
Language英語
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Cited Times [WOS]:4   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionUniversity of Macau
AffiliationFudan University
Recommended Citation
GB/T 7714
Wang Y.,Chen W.-N.,Wang X.-W.,et al. The hardware thread interface design and adaptation on dynamically reconfigurable SoC[C],2009:173-178.
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