Please use this identifier to cite or link to this item: http://repository.umac.mo/handle/10692/926
Title: A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS
Authors: Zhu, Yan (朱燕)
Chan, Chi Hang (陳知行)
Chio, U Fat
Sin, Sai Weng (冼世榮)
U, Seng Pan (余成斌)
Martins, Rui Paulo Da Silva (馬許願)
Maloberti, Franco
Issue Date: Jun-2010
Citation: IEEE Journal of Solid-State Circuits (SCI, IF=3.22), Jun. 2010, v.45, p. 1111-1121
Abstract: A 1.2 V 10-bit 100MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes reset time for the preamplifier to improve the conversion speed. Measurement results on a 90nm CMOS prototype operated at 1.2V supply show 3mW total power consumption with a peak SNDR of 56.6dB and a FOM of 77fJ/conv-step.
URI: http://hdl.handle.net/10692/926
ISSN: 0018-9200
Keywords: Analog-to-digital converter
ADC
SAR
Charge-recovery
Switched technique
Access: http://dx.doi.org/ 10.1109/JSSC.2010.2048498
Appears in Collections:ECE Journal Articles

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