Please use this identifier to cite or link to this item:
Title: Ultra-area-efficient three-stage amplifier using current buffer Miller compensation and parallel compensation
Authors: Yan, Zu Shu (嚴祖樹)
Mak, Pui In (麥沛然)
Law, Man Kay (羅文基)
Martins, Rui Paulo Da Silva
Issue Date: Sep-2012
Publisher: IEEE
Citation: IET Electronics Letters, 24 May 2012, v. 48, no. 11, p. 624-626
Abstract: An ultra-compact three-stage amplifier is proposed by merging current buffer Miller compensation with parallel compensation, which achieves significant improvement in area efficiency without sacrificing the gain-bandwidth product (GBW) and power. Fabricated in 0.35 mm CMOS the amplifier measures 4.98 MHz GBW at 150 pF load while drawing 20 uA at 2 V. The entailed compensation capacitance is minimised to 1.5 pF and the chip size is merely 0.012 mm2.
ISSN: 0013-5194
Keywords: Three-stage amplifier
Frequency compensation

Files in This Item:
File Description SizeFormat 
06204268.pdf201.43 kBAdobe PDFView/Open
Appears in Collections:OTHERS Journal Articles

Items in UMIR are protected by copyright, with all rights reserved, unless otherwise indicated.