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Title: A 0.016mm2 144µW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW
Authors: Mak, Pui In (麥沛然)
Issue Date: Feb-2013
Publisher: IEEE
Citation: IEEE journal of solid-state circuits, Feb. 2013, v. 48, no. 2, pp. 527-540
Abstract: A 0.016-mm2 144-µW three-stage amplifier capable of driving 1-to-15-nF capacitive load (CL) is described. It is optimized via combining current-buffer Miller compensation and parasitic-pole cancellation (via an active left-hand-plane zero circuit) to extend the C¬¬L drivability with small power and area. Fabricated in 0.35-µm CMOS, the gain-bandwidth product (GBW), slew rate (SR) and phase margin measured over 1-to-15-nF CL are minimally 0.95 MHz, 0.22 V/µs and 52.3o, respectively. The results at 15-nF CL correspond to 4.48x-improved small-signal FOMS (= GBW ∙ CL / Power), and 2.55x-improved large-signal FOML (= SR ∙ CL / Power) with respect to the prior arts. The sizing and optimization are systematically guided by the Local-Feedback Loop Analysis. It is an insightful control-centric method upgrading the pole-zero placements to a more discerning and comparable system level.
ISSN: 0018-9200
Keywords: Active LHP zero
Miller compensation
Current buffer
Buffermiller compensation
Pole-zero cancellation
Three-stage amplifier
Access: View full-text via DOI

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