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Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications
Chio-In Ieong; Mingzhong Li; Man-Kay Law; Pui-In Mak; Mang-I Vai; Peng-Un Mak; Feng Wan; Rui P. Martins
2013
Conference NameIEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)
Source Publication2013 IEEE International Conference of Electron Devices and Solid-state Circuits
Conference Date3-5 June 2013
Conference PlaceHong Kong, PEOPLES R CHINA
Abstract

This paper reports the design and optimization of a standard cell library in 0.18μm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage 1.8V and re-characterized 0.6V. © 2013 IEEE.

DOIhttp://doi.org/10.1109/EDSSC.2013.6628062
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000380585600032
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Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
AffiliationState Key Lab of Analog and Mixed-Signal VLSI and FST/ECE, University of Macau, Macau, China
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chio-In Ieong,Mingzhong Li,Man-Kay Law,et al. Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications[C],2013.
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