Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications | |
Chio-In Ieong; Mingzhong Li; Man-Kay Law![]() ![]() ![]() ![]() ![]() ![]() | |
2013 | |
Conference Name | IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) |
Source Publication | 2013 IEEE International Conference of Electron Devices and Solid-state Circuits |
Conference Date | 3-5 June 2013 |
Conference Place | Hong Kong, PEOPLES R CHINA |
Abstract | This paper reports the design and optimization of a standard cell library in 0.18μm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage 1.8V and re-characterized 0.6V. © 2013 IEEE. |
DOI | http://doi.org/10.1109/EDSSC.2013.6628062 |
URL | View the original |
Indexed By | SCI |
Language | 英语 |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000380585600032 |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Affiliation | State Key Lab of Analog and Mixed-Signal VLSI and FST/ECE, University of Macau, Macau, China |
First Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Chio-In Ieong,Mingzhong Li,Man-Kay Law,et al. Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications[C],2013. |
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