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A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
Chan, Chi-Hang1; Zhu, Yan1; Zhang, Wai-Hong1; Seng-Pan, U.1,2; Martins, Rui Paulo1,3
2018-03
Source PublicationIEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN0018-9200
Volume53Issue:3Pages:850-860
Abstract

This paper presents a 2x time-interleaved 7-b 2.4-GS/s 1-then-2 bicycle SAR ADC in 28-nm CMOS. The process-voltage-temperature sensitivity of a multi-bit SAR architecture has been improved by the proposed 1-then-2 bicycle scheme with background offset calibration. With the pre-charge reduction scheme, the traditional large switching energy and time consuming pre-charge operation have been removed, which simultaneously enables a simple control logic without the need of a V-cm voltage. Besides, a background offset calibration is implemented on chip which does not involve any extra phase or calibration input signal. Its operation is well embedded within the 1-then-2 bicycle architecture, thus leading to a very minimal modification of the ADC core. With an improved fringing DAC structure and a high-speed dynamic logic circuit, a single-channel ADC can work at 1.2 GS/s under a 0.9-V supply. Using two-way time interleaving, the prototype samples at 2.4 GHz and consumes 5-mW power including the on-chip background offset calibration. It exhibits a 40.05-dB SNDR at Nyquist, leading to a Walden FoM of 25.3 fJ/conversion step. Measurement results show that the SNDR of the ADC can be kept above 38 dB at 2 GS/s under a wide range of temperature, supply, and input common-mode variation.

Keyword1-then-2 B/cycle Sar Adc Analog-to-digital Conversion Background Offset Calibration Multi-bit/cycle Sar Adc Time Interleaving
DOI10.1109/JSSC.2017.2785349
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000426009800016
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
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Citation statistics
Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China
2.Synopsys Macau Ltd., Macau, China
3.on leave from the Instituto Superior Técnico (IST)/Universidade de Lisboa, 1649-004 Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chan, Chi-Hang,Zhu, Yan,Zhang, Wai-Hong,et al. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS,2018,53(3):850-860.
APA Chan, Chi-Hang,Zhu, Yan,Zhang, Wai-Hong,Seng-Pan, U.,&Martins, Rui Paulo.(2018).A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration.IEEE JOURNAL OF SOLID-STATE CIRCUITS,53(3),850-860.
MLA Chan, Chi-Hang,et al."A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration".IEEE JOURNAL OF SOLID-STATE CIRCUITS 53.3(2018):850-860.
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