Please use this identifier to cite or link to this item: http://repository.umac.mo/handle/10692/643
Title: A 1.2-V 10-bit 60-360MS/s time-interleaved pipelined ADC in 0.18µm CMOS with minimized supply headroom
Authors: Sin, Sai Weng (冼世榮)
U, Seng Pan (余成斌)
Martins, Rui Paulo Da Silva (馬許願)
Issue Date: Jan-2010
Publisher: IET Circuits, Devices & Systems
Citation: IET Journal - IET circuits, devices and systems, Jan. 2010, v. 4, no. 1, p. 1-13
Abstract: A low-voltage 1.2-V 10-bit 60 – 360 MS/s 6 channels time-interleaved reset-opamp pipelined ADC is designed and implemented in 0.18 µm CMOS (VTHN / VTHP = 0.63 V/-0.65 V for mid-supply floating switches). Without using on-chip high-voltage and low-VT options, the proposed ADC employs low-voltage resistive-demultiplexing techniques, low-voltage gain-and-offset compensation, feedback current biasing to reduce the sensitivity of the bias current over process variations, and current-mode sub-ADCs with static current sharing for a low-voltage time-interleaved implementation. Speed options of 60-360MS/s are available with scalable power and they can be obtained by automatic selection of the number of time-interleaved channels. The chip measurement results show that the ADC exhibits a DNL/INL better than 0.9/1.2 LSB and a peak SNDR above 54 dB, for all speed options, while consuming 85 mW at 60 MS/s and 426 mW at 360 MS/s. The active die area is 13.2 mm2
URI: http://hdl.handle.net/10692/643
ISSN: 1751-858X
Keywords: analog IC design
analog-to-digital converter
low-voltage
time-interleaved
Access: http://dx.doi.org/10.1049/iet-cds.2008.0229
Appears in Collections:ECE Journal Articles

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