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A 0.024mm28b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS
Wei, Hegong1; Chan, Chi-Hang1; Chio, U.-Fat1; Sin, Sai-Weng1; Seng-Pan, U.1; Martins, Rui1,2; Maloberti, Franco3
2011
Source PublicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages188-189
Author of SourceInstitute of Electrical and Electronics Engineers Inc.
AbstractThe successive-approximation (SA) algorithm is traditionally used for low-bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions [1]. This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Key features of the architecture are a resistive DAC and a 2b-per-cycle conversion with interpolated sampling front-ends and shift registers. A cross-coupled bootstrapping network is also implemented to alleviate the signal-dependent clock feed-through. The very compact layout leads to a silicon area of 0.024 mm2. © 2011 IEEE.
DOI10.1109/ISSCC.2011.5746276
Language英语
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Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Affiliation1.University of Macau, China;
2.Instituto Superior Tecnico, Lisbon, Portugal;
3.University of Pavia, Pavia, Italy
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Wei, Hegong,Chan, Chi-Hang,Chio, U.-Fat,et al. A 0.024mm28b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS[C]//Institute of Electrical and Electronics Engineers Inc.,2011:188-189.
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