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A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
Chi-Hang Chan1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan U1,3; R. P. Martins1,2
2015-03-17
Conference Name62nd IEEE International Solid-State Circuits Conference (ISSCC)
Source Publication2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
Volume58
Pages466-467
Conference Date22-26 Feb. 2015
Conference PlaceSan Francisco, CA, United states
Author of SourceInstitute of Electrical and Electronics Engineers Inc.
Other Abstract

Communication devices such as 60GHz-band receivers and serial links demand power-efficient low-resolution gigahertz-sampling-rate ADCs. However, the energy efficiency of ADCs is degraded by scaling up transistor widths in the building blocks for high speed, thus increasing the impact of intrinsic parasitics. Parallel schemes like multi-bit processing and interleaving [1], can ease the problems caused by scaling and lead to better efficiency if the hardware overhead is wisely reduced [2]. This paper presents a combination of 4× time interleaving and 3b/cycle multi-bit SAR ADC in 65nm CMOS, achieving a Nyquist FoM of 39fJ/conv-step for 5GS/s at 1V supply. © 2015 IEEE.

DOIhttp://doi.org/10.1109/ISSCC.2015.7063128
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000355252700198
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Citation statistics
Cited Times [WOS]:12   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.University of Macau, Macao, China;
2.Synopsys, Macao, China;
3.Instituto Superior Tecnico, Universidade de Lisboa, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chi-Hang Chan,Yan Zhu,Sai-Weng Sin,et al. A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS[C]//Institute of Electrical and Electronics Engineers Inc.,2015:466-467.
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