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A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration
Chi-Hang Chan1; Yan Zhu1; Iok-Meng Ho1; Wai-Hong Zhang1; Seng-Pan U1,2; Rui Paulo Martins1,3
2017-03-02
Conference Name64th IEEE International Solid-State Circuits Conference (ISSCC)
Source Publication2017 IEEE International Solid-State Circuits Conference (ISSCC)
Volume60
Pages282-283
Conference Date5-9 Feb. 2017
Conference PlaceSan Francisco, CA
CountryUSA
Author of SourceInstitute of Electrical and Electronics Engineers Inc.
Other Abstract

Wireless communication systems and Ethernet networks call for moderate-resolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardware reduction techniques, there are still a few limitations that restrain this architecture. First, the pre-charge slows down the logic and the DAC settling, especially during the MSB conversions. Second, unlike the offset among sub-channels of interleaving SAR ADCs, which can be easily calibrated in the background at the ADC backend [2], the offsets of the comparators in multi-bit SAR ADCs lead to a large sub-ranging error. Such offset is often calibrated in the foreground [1][3] but cannot track voltage and temperature (V&T) variations. This paper presents a 1-then-2b/cycle SAR architecture which removes conventional pre-charging and simultaneously minimizes the logic circuitry complexity to that of a 1b/cycle SAR. The comparator offsets are calibrated in the background without any extra phases or input references. With 2× time interleaving, the prototype achieves 2.4GS/s using a 0.9V supply in 28nm CMOS, leading to a 25.3fJ/conv-step Walden FoM at Nyquist input.

DOIhttp://doi.org/10.1109/ISSCC.2017.7870371
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000403393800116
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Citation statistics
Cited Times [WOS]:14   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.University of Macau, Macao, China
2.Synopsys Macau Ltd, Macao, China
3.Instituto Superior Tecnico/University of Lisboa, Lisboa, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chi-Hang Chan,Yan Zhu,Iok-Meng Ho,et al. A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration[C]//Institute of Electrical and Electronics Engineers Inc.,2017:282-283.
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