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A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM
Yang, Shiheng1; Yin, Jun1; Mak, Pui-In1; Martins, Rui P.1,2
2018-03-08
Conference Name65th IEEE International Solid-State Circuits Conference, ISSCC 2018
Source PublicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume61
Pages118-120
Conference Date2 11, 2018 - 2 15, 2018
Conference PlaceSan Francisco, CA, United states
Author of SourceInstitute of Electrical and Electronics Engineers Inc.
AbstractMultiplying delay-locked loops (MDLL) and injection-locked clock multipliers (ILCM) have shown improved jitter performance in recent years [1-5], but their PLL-based frequency-tracking loops (FTLs) for securing performance against frequency and PVT variations are area and power hungry. In [1], the frequency (FOUT) is tracked by a replica-delay cell of the VCO, such that the intrinsic phase information is preserved under reference injection (REF-INJ). Regrettably an analog FTL is susceptible to noise and mismatch from the charge pump, demanding more area (loop filter: 0.01mm2) and power (charge pump: 0.8mW) to limit the in-band jitter deterioration. © 2018 IEEE.
DOI10.1109/ISSCC.2018.8310212
Language英语
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Document TypeConference paper
CollectionUniversity of Macau
Affiliation1.University of Macau, China;
2.Instituto Superior Tecnico, University of Lisboa, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Yang, Shiheng,Yin, Jun,Mak, Pui-In,et al. A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM[C]//Institute of Electrical and Electronics Engineers Inc.,2018:118-120.
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