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A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS
Chi-Hang Chan1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan U1,2; Rui Paulo Martins1,3; Franco Maloberti1,4
2013
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume48Issue:9Pages:2154-2169
Abstract

This paper presents a 5-bit 1.25-GS/s folding flash ADC. The prototype achieves a folding factor of four with a capacitive folding technique that only consumes dynamic power. Incorporated with various calibration schemes, folding errors and the comparator's threshold inaccuracies are corrected, thus allowing a low input capacitance of 80 fF. The design is fabricated using 65-nm digital CMOS technology and occupies 0.007 mm2. The maximum DNL and INL post calibration are 0.67 and 0.47 LSB, respectively. Measurement results show that the ADC can achieve 1.25 GS/s at 1-V supply with a total power consumption of 595 μW. In addition, it exhibits a mean ENOB of 4.8b at dc among ten chips, which yields an FoM of 17 fJ/conversion-step. © 1966-2012 IEEE.

KeywordAnalog-to-digital Conversion (Adc) Calibration Embedded Reference Flash Adc Folding Low Power
DOIhttp://doi.org/10.1109/JSSC.2013.2264617
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000323651000017
The Source to ArticleScopus
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Citation statistics
Cited Times [WOS]:10   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorChi-Hang Chan
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China
2.the Synopsys-Chipidea Microelectronics (Macau) Limited
3.on leave from Instituto Superior Técnico/Technical University of Lisbon, 1049-001 Lisbon, Portugal
4.Department of Electronics, University of Pavia, 27100 Pavia, Italy
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Chi-Hang Chan,Yan Zhu,Sai-Weng Sin,et al. A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits,2013,48(9):2154-2169.
APA Chi-Hang Chan,Yan Zhu,Sai-Weng Sin,Seng-Pan U,Rui Paulo Martins,&Franco Maloberti.(2013).A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS.IEEE Journal of Solid-State Circuits,48(9),2154-2169.
MLA Chi-Hang Chan,et al."A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS".IEEE Journal of Solid-State Circuits 48.9(2013):2154-2169.
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