UM  > 微電子研究院
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation
Yan Zhu1,2; Chi-Hang Chan1,2; Sai-Weng Sin1,2; Seng-Pan U1,2,3; Rui Paulo Martins1,2; Franco Maloberti1,2,4
2012
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume47Issue:11Pages:2614-2626
Abstract

This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip-around operation. A capacitive attenuation used in both the first and second DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is discussed, and the possible limits caused by nonidealities are analyzed for a proper correction in the design. These include the inter-stage-gain error and various channel mismatches of offset, gain, and timing. Measurements of a 65-nm CMOS prototype operating at 160 MS/s and 1.1-V supply show an SNDR of 55.4 dB and 2.72 mW total power consumption. © 2012 IEEE.

KeywordDecoupled Flip-around Mdac Offset-cancellation Pipelined-sar Adc Vdd -attenuator
DOIhttp://doi.org/10.1109/JSSC.2012.2211695
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000310888200007
The Source to ArticleScopus
Fulltext Access
Citation statistics
Cited Times [WOS]:21   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorYan Zhu; Seng-Pan U
Affiliation1.the State-Key Laboratory of Analog and Mixed Signal VLSI
2.the Faculty of Science and Technology, University of Macau, Macao, China
3.Synopsys-Chipidea Microelectronics (Macau) Ltd
4.the University of Pavia, Pavia, Italy
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Yan Zhu,Chi-Hang Chan,Sai-Weng Sin,et al. A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation[J]. IEEE Journal of Solid-State Circuits,2012,47(11):2614-2626.
APA Yan Zhu,Chi-Hang Chan,Sai-Weng Sin,Seng-Pan U,Rui Paulo Martins,&Franco Maloberti.(2012).A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation.IEEE Journal of Solid-State Circuits,47(11),2614-2626.
MLA Yan Zhu,et al."A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation".IEEE Journal of Solid-State Circuits 47.11(2012):2614-2626.
Related Services
Recommend this item
Bookmark
Usage statistics
Export to Endnote
Google Scholar
Similar articles in Google Scholar
[Yan Zhu]'s Articles
[Chi-Hang Chan]'s Articles
[Sai-Weng Sin]'s Articles
Baidu academic
Similar articles in Baidu academic
[Yan Zhu]'s Articles
[Chi-Hang Chan]'s Articles
[Sai-Weng Sin]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[Yan Zhu]'s Articles
[Chi-Hang Chan]'s Articles
[Sai-Weng Sin]'s Articles
Terms of Use
No data!
Social Bookmark/Share
All comments (0)
No comment.
 

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.