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An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac
Hegong Wei1; Chi-Hang Chan1; U-Fat Chio1; Sai-Weng Sin1; Seng-Pan U1; Rui Paulo Martins1,2; Franco Maloberti1,3
2012
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume47Issue:11Pages:2763-2772
Abstract

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integratedcircuit implementation, the proposed SAR ADC achievesrapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400MS/s from 1.2-V supply and 42 fJ/conversion-step at 250MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm .© 1966-2012 IEEE.

Keyword2-b-per-cycle (2 B/c) Analog-to-digital Converter (Adc) Resistive Dac Successive Approximation Register (Sar)
DOIhttp://doi.org/10.1109/JSSC.2012.2214181
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000310888200019
The Source to ArticleScopus
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Cited Times [WOS]:51   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
Corresponding AuthorHegong Wei
Affiliation1.State Key Lab of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China
2.on leave from Instituto Superior Técnico/TU, Lisbon, Portugal
3.University of Pavia, 27100 Pavia, Italy
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Hegong Wei,Chi-Hang Chan,U-Fat Chio,et al. An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac[J]. IEEE Journal of Solid-State Circuits,2012,47(11):2763-2772.
APA Hegong Wei.,Chi-Hang Chan.,U-Fat Chio.,Sai-Weng Sin.,Seng-Pan U.,...&Franco Maloberti.(2012).An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac.IEEE Journal of Solid-State Circuits,47(11),2763-2772.
MLA Hegong Wei,et al."An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac".IEEE Journal of Solid-State Circuits 47.11(2012):2763-2772.
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