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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
Zhu Y.; Chan C.-H.; Chio U.-F.; Sin S.-W.; U S.-P.; Martins R.P.; Maloberti F.
2010
Source PublicationIEEE Journal of Solid-State Circuits
ISSN189200
Volume45Issue:6Pages:1111
AbstractA 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step. © 2006 IEEE.
KeywordCharge-recovery Reference-free Switched technique
DOI10.1109/JSSC.2010.2048498
URLView the original
Language英语
The Source to ArticleScopus
Citation statistics
Cited Times [WOS]:281   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Recommended Citation
GB/T 7714
Zhu Y.,Chan C.-H.,Chio U.-F.,et al. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS[J]. IEEE Journal of Solid-State Circuits,2010,45(6):1111.
APA Zhu Y..,Chan C.-H..,Chio U.-F..,Sin S.-W..,U S.-P..,...&Maloberti F..(2010).A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS.IEEE Journal of Solid-State Circuits,45(6),1111.
MLA Zhu Y.,et al."A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS".IEEE Journal of Solid-State Circuits 45.6(2010):1111.
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