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N-bits successive approximation register analog-to-digital converting circuit
Yan Zhu; Chi Hang Chan; U Fat Chio; Sai Weng Sin;; Seng Pan U; Rui Paulo Da Silva Martins; Franco Maloberti
Rights HolderUNIVERSITY OF MACAU
Date Available2013
CountryUnited States
Subtype发明专利
Abstract

The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising : an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

Application Date2011-06-01
Patent NumberUS8344931B2
Language英语
Application NumberUS13150508
Open (Notice) NumberUS8344931B2
Fulltext Access
Document TypePatent
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INSTITUTE OF MICROELECTRONICS
AffiliationUniversity of Macau
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Yan Zhu,Chi Hang Chan,U Fat Chio,et al. N-bits successive approximation register analog-to-digital converting circuit. US8344931B2.
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