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A 0.0056mm(2) All-Digital MDLL Using Edge Re-Extraction, Dual-Ring VCOs and a 0.3mW Block-Sharing Frequency Tracking Loop Achieving 292fs(rms) Jitter and-249dB FOM
Yang, Shiheng; Yin, Jun; Mak, Pui-In; Martins, Rui P.; IEEE
2018
Conference Name2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC)
Publication Place345 E 47TH ST, NEW YORK, NY 10017 USA
PublisherIEEE
URLView the original
Indexed ByCPCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000432256300041
The Source to ArticleWOS
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Document TypeConference paper
CollectionUniversity of Macau
Recommended Citation
GB/T 7714
Yang, Shiheng,Yin, Jun,Mak, Pui-In,et al. A 0.0056mm(2) All-Digital MDLL Using Edge Re-Extraction, Dual-Ring VCOs and a 0.3mW Block-Sharing Frequency Tracking Loop Achieving 292fs(rms) Jitter and-249dB FOM[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2018.
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