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A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS
Zhu, Yan; Chan, Chi-Hang; Zheng, Zi-Hao; Li, Cheng; Zhong, Jian-Yu; Martins, Rui P.
2018-11
Conference NameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume65
Issue11
Pages3606-3616
Publication Place445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
AbstractThis paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @ Nyquist leading to a FOM of 69 fJ/conv.step.
KeywordTime-interleaved ADC sampling front-end design passive sharing pipelined-SAR ADC switch bootstrap technique
DOI10.1109/TCSI.2018.2859027
URLView the original
Indexed BySCI ; CPCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000446922100002
The Source to ArticleWOS
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Cited Times [WOS]:2   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionUniversity of Macau
Recommended Citation
GB/T 7714
Zhu, Yan,Chan, Chi-Hang,Zheng, Zi-Hao,et al. A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS[C]. 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC,2018:3606-3616.
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