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A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
Zhu, Yan; Chan, Chi-Hang; Pan, Seng U.; Martins, Rui Paulo
2017-01
Source PublicationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN1063-8210
Volume25Issue:1Pages:354-363
Abstract

A 10-bit 500-MS/s partial-interleaving pipelined successive approximation register (SAR) analog-to-digital converter (ADC) architecture is presented that implements a full-speed 2-bit/cycle SAR at the front end with interleaved residue MDACs and SAR ADCs at the back end. This architecture achieves high speed, while preventing the interleaving spurs. In addition, the design considerations and calibration techniques for gain and offset are also introduced. A histogram stage gain error (HSGE) calibration is implemented to correct the conversion nonlinearities in the digital domain. Measurement results on a 65-nm CMOS prototype show an signal-to-noise distortion ratio (SNDR) of 55.9 dB at dc input and a figure of merit (FoM) of 32 fJ/conversion step at 1.2 V supply.

KeywordOffset Calibration Partial Interleaving (Pi) Pipelined-sar Stage-gain Error Calibration
DOI10.1109/TVLSI.2016.2576468
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000394591600029
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
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Cited Times [WOS]:6   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Corresponding AuthorZhu, Yan; Chan, Chi-Hang; Pan, Seng U.; Martins, Rui Paulo
AffiliationState Key Laboratory of Analog and Mixed Signal, University of Macau, Macau, China
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Zhu, Yan,Chan, Chi-Hang,Pan, Seng U.,et al. A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2017,25(1):354-363.
APA Zhu, Yan,Chan, Chi-Hang,Pan, Seng U.,&Martins, Rui Paulo.(2017).A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,25(1),354-363.
MLA Zhu, Yan,et al."A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25.1(2017):354-363.
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