Please use this identifier to cite or link to this item: http://repository.umac.mo/handle/10692/2383
Title: Pre-emphasis transmitter (0.007 mm2, 8 Gbit/s, 0-14 dB) with improved data zero-crossing accuracy in 65 nm CMOS
Authors: Mak, Pui In (麥沛然)
Y. Chen
L. Zhang
H. Qian
Y. Wang
Issue Date: 18-Jul-2013
Publisher: Institution of Engineering and Technology - IET
Citation: Electronics Letters, Jul 2013, Vol. 49, Issue 15, p. 929-930.
Abstract: A pre-emphasis transmitter with improved data zero-crossing accuracy is described. It is achieved via data re-synchronisation using a set of extended true single-phase clock latches before output combining, constituting a robust, area- and power-efficient solution. Fabricated in 65 nm CMOS, the full-rate one-tap pre-emphasis transmitter measures a total jitter of 33.12 ps up to an 8 Gbit/s data rate, and 25.04 to 38.75 ps under a 0-14 dB reconfigurable pre-emphasis range. The achieved output swing is as large as 550 mVpp, and the active area is just 0.007 mm2.
URI: http://hdl.handle.net/10692/2383
ISSN: 0013-5194
1350-911X
Keywords: CMOS integrated circuits
Clocks
Flip-flops
Access: View full-text via DOI

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