Please use this identifier to cite or link to this item:
Title: A 0.016-mm2 144-μ W Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW
Authors: Yan, Zushu
Mak, Pui In (麥沛然)
Law, Man Kay (羅文基)
Martins, Rui Paulo Da Silva
Issue Date: 1-Feb-2013
Publisher: IEEE
Citation: IEEE Journal of Solid-State Circuits, Feb 2013, Vol. 48, Issue 2, p. 527-540
Abstract: A 0.016-mm2 144-μ W three-stage amplifier capable of driving 1-to-15-nF capacitive load (CL) is described. It is optimized via combining current-buffer Miller compensation and parasitic-pole cancellation (via an active left-half-plane zero circuit) to extend the CL drivability with small power and area. Fabricated in 0.35-μ m CMOS, the minimum gain-bandwidth product (GBW), slew rate (SR) and phase margin measured over 1-to-15-nF CL are 0.95 MHz, 0.22 V/ μs and 52.3 °, respectively. The results at 15-nF CL correspond to 2.02x-improved small-signal FOMS (=GBW·CL/Power), and 1.44x-improved large-signal FOML (=SR·CL/Power) with respect to prior art. The sizing and optimization are systematically guided by Local Feedback Loop Analysis. It is an insightful control-centric method allowing the pole-zero placements to be more analyzable and comparable at the system level.
ISSN: 0018-9200
Keywords: Active LHP zero
Pole-zero cancellation
Current buffer
Current buffer Miller compensation
Frequency compensation
Miller compensation
Three-stage amplifier
Access: View full-text via DOI

Files in This Item:
File Description SizeFormat 
11158_0_3-stageamp_JSSC2013.pdf3.68 MBAdobe PDFView/Open
Appears in Collections:OTHERS Journal Articles

Items in UMIR are protected by copyright, with all rights reserved, unless otherwise indicated.