Please use this identifier to cite or link to this item: http://repository.umac.mo/handle/10692/2235
Title: A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC
Authors: Zhu, Yan (諸嫣)
Wong, Si-Seng
Chio, U-Fat
Sin, Sai-Weng
Martins, Rui Paulo
U, Seng-Pan
Issue Date: 20-May-2013
Publisher: IEEE Computer Society
Citation: Solid-State Circuits, IEEE Journal of Solid-State Circuits, May 2013, Vol. 48, Issue 8, p.1783 - 1794.
Abstract: This paper presents the architecture of a 10b 170MS/stwo-step binary-search assisted time-interleaved SAR ADC. Thefront-end stage of this ADC is built with a 5b binary-search ADC,which is shared by two time-interleaved 6b SAR ADCs in thesecond-stage. The design does not use any static component suchas op-amp or preamplifier that causes large dissipation of staticpower. DAC settling speed and power are also relaxed thanks tothis architecture. Besides, the process insensitive asynchronouslogic further reduces the delay of SA loop rather than using worstcase delay cells to compensate the process variation problem. TheADC was fabricated in 65 nm CMOS and achieves 54.6 dB SNDRat 170 MS/s with only 2.3 mW of power consumption, leading to aFoM of 30.8 fJ/conversion-step.
URI: http://hdl.handle.net/10692/2235
ISSN: 0018-9200
Keywords: Two-Step
Binary-Search ADC
Analog-to-digital converter (ADC)
Binary-search ADC
SAR ADC
Time-interleaved
Access: http://dx.doi.org/10.1109/JSSC.2013.2258832
Appears in Collections:OTHERS Journal Articles

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