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A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures
Ieong, Chio-In1; Li, Mingzhong1; Law, Man-Kay2; Mak, Pui-In1; Vai, Mang I.1; Martins, Rui P.1
2017-04
Source PublicationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN1063-8210
Volume25Issue:4Pages:1307-1319
Abstract

This paper presents a real-time electrocardiogram (ECG) data compression processor with improved energy efficiency while maintaining high accuracy and real-time operation. Wavelet shrinkage is exploited to filter the noise and achieve sparse ECG signal representation. Adaptive temporal decimation is proposed to achieve configurable processing to adaptively reduce the data amount and computational activities for further power reduction. Modified Huffman and run-length wavelet source coding (MHRLC) is also designed to represent wavelet coefficients with optimized average code length and reduced memory requirement. Fabricated in 0.18-mu m CMOS, the ECG processor is implemented with customized near-threshold digital logics for minimum energy operation. The prototype was fully validated with the MIT-BIH Arrhythmia database. With a power consumption of 147-375 nW at 0.45 V, the proposed ECG processor exhibits a wide compression ratio ranging from 2.89 to 26.91, corresponding to a percentage-RMS-distortion from 0% to 3.11%.

KeywordAdaptive Temporal Decimation (Atd) Data Compression Processor Electrocardiogram (Ecg) Near-threshold Digital Logics Wavelet Shrinkage (Ws) Wavelet Transform (Wt)
DOI10.1109/TVLSI.2016.2638826
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000398858800011
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
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Cited Times [WOS]:13   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Corresponding AuthorLaw, Man-Kay
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macau, China
2.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Ieong, Chio-In,Li, Mingzhong,Law, Man-Kay,et al. A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2017,25(4):1307-1319.
APA Ieong, Chio-In,Li, Mingzhong,Law, Man-Kay,Mak, Pui-In,Vai, Mang I.,&Martins, Rui P..(2017).A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,25(4),1307-1319.
MLA Ieong, Chio-In,et al."A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25.4(2017):1307-1319.
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