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Complex-pole load offering concurrent image rejection and channel selection
Zhicheng Lin; Pui-In Mak; Rui Paulo da Silva Martins
2016-10-25
Rights HolderUNIVERSITY OF MACAU
Date Available2016-10-25
CountryUnited States
Subtype发明专利
Abstract

complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative IF (?IF) for channel selection and image rejectionoffering image rejection and channel selection concurrently.

Application Date2014-04-17
Patent NumberUS9479140B2
Language英语
Application NumberUS14255094
Open (Notice) NumberUS9479140B2
Fulltext Access
Document TypePatent
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
AffiliationUNIVERSITY OF MACAU
Recommended Citation
GB/T 7714
Zhicheng Lin,Pui-In Mak,Rui Paulo da Silva Martins. Complex-pole load offering concurrent image rejection and channel selection. US9479140B2[P]. 2016-10-25.
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