UM
A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC
Zhong, Jianyu; Zhu, Yan; Chan, Chi-Hang; Sin, Sai-Weng; U, Seng-Pan; Martins, Rui Paulo
2017-07
Source PublicationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN1549-8328
Volume64Issue:7Pages:1684-1695
AbstractThis paper presents a 12b 180 MS/s 0.068 mm(2) 2x time-interleaved pipelined-SAR analog-to-digital converter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a compact area. We improve the noise performance by implementing a merged-residue- DAC operation in the first-stage ADC. Also, we propose a dual-phase bootstrap technique to improve the sampling linearity in the partial interleaving architecture. The measurement results of the ADC prototype in 65 nm CMOS demonstrate the effectiveness of the proposed calibration through the enhancement of the signal to noise-and-distortion ratio from 51.5 to 60.9 dB at a Nyquist input, leading to a FoM@Nyq of 36.7 fJ/conversion-step.
KeywordAnalog-to-digital converter (ADC) successive approximation architecture low power switched-capacitor circuits
DOI10.1109/TCSI.2017.2679748
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000404294900005
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
Fulltext Access
Citation statistics
Cited Times [WOS]:9   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Recommended Citation
GB/T 7714
Zhong, Jianyu,Zhu, Yan,Chan, Chi-Hang,et al. A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2017,64(7):1684-1695.
APA Zhong, Jianyu,Zhu, Yan,Chan, Chi-Hang,Sin, Sai-Weng,U, Seng-Pan,&Martins, Rui Paulo.(2017).A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,64(7),1684-1695.
MLA Zhong, Jianyu,et al."A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 64.7(2017):1684-1695.
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