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Local silicon-gate carbon nanotube field effect transistors using silicon-on-insulator technology
Zhang M.; Chan P.C.H.; Chai Y.; Liang Q.; Tang Z.K.
2006-07-24
Source PublicationApplied Physics Letters
ISSN00036951
Volume89Issue:2
AbstractA local silicon-gate carbon nanotube field effect transistor (CNFET) configuration has been proposed and implemented for integration purpose. By combining the advantages of in situ carbon nanotube growth technology and the silicon-on-insulator technology, we have realized the CNFETs with individual device operation, low parasitic capacitance, high yield fabrication, and better compatibility to the complementary-metal-oxide-semiconductor (CMOS) process. The CNFETs show up-to-date electrical performance. The scaling effect of gate oxide is also explored. This configuration makes CNFET a step closer to the CMOS integrated circuit application. © 2006 American Institute of Physics.
DOI10.1063/1.2221515
URLView the original
Language英語
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Cited Times [WOS]:13   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
AffiliationHong Kong University of Science and Technology
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GB/T 7714
Zhang M.,Chan P.C.H.,Chai Y.,et al. Local silicon-gate carbon nanotube field effect transistors using silicon-on-insulator technology[J]. Applied Physics Letters,2006,89(2).
APA Zhang M.,Chan P.C.H.,Chai Y.,Liang Q.,&Tang Z.K..(2006).Local silicon-gate carbon nanotube field effect transistors using silicon-on-insulator technology.Applied Physics Letters,89(2).
MLA Zhang M.,et al."Local silicon-gate carbon nanotube field effect transistors using silicon-on-insulator technology".Applied Physics Letters 89.2(2006).
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