UM
Novel local silicon-gate carbon nanotube transistors combining silicon-on-insulator technology for integration
Zhang M.1; Chan P.C.H.1; Chai Y.1; Liang Q.1; Tang Z.K.1
2009-03-01
Source PublicationIEEE Transactions on Nanotechnology
ISSN1536125X
Volume8Issue:2Pages:260-268
AbstractBy taking advantage of the silicon-on-insulator technology and the in situ carbon nanotube (CNT) growth, new local silicon-gate carbon nanotube FETs (CNFETs) have been implemented in this paper. We propose an approach to integrate the CNFET onto the silicon CMOS platform for the first time. Individual device operation, batch fabrication, low parasitic capacitance, and better compatibility to the CMOS process were realized. The characteristics of the CNFETs are comparable to the state-of-the-art devices reported. The scaling effect, ambipolar conductance, Schottky barrier effect, and IV characteristics noise were analyzed. The physical properties of the CNTs were also characterized. © 2006 IEEE.
KeywordCarbon nanotube (CNT) Carbon nanotube FET (CNFET) Integration Nanotechnology Silicon-on-insulator (SOI)
DOI10.1109/TNANO.2008.2011773
URLView the original
Language英語
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Cited Times [WOS]:6   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.Hong Kong University of Science and Technology
2.Shenzhen HYB Battery Company Ltd.
3.Solomon Systech Limited
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GB/T 7714
Zhang M.,Chan P.C.H.,Chai Y.,et al. Novel local silicon-gate carbon nanotube transistors combining silicon-on-insulator technology for integration[J]. IEEE Transactions on Nanotechnology,2009,8(2):260-268.
APA Zhang M.,Chan P.C.H.,Chai Y.,Liang Q.,&Tang Z.K..(2009).Novel local silicon-gate carbon nanotube transistors combining silicon-on-insulator technology for integration.IEEE Transactions on Nanotechnology,8(2),260-268.
MLA Zhang M.,et al."Novel local silicon-gate carbon nanotube transistors combining silicon-on-insulator technology for integration".IEEE Transactions on Nanotechnology 8.2(2009):260-268.
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