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A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC
Chan, Chi-Hang1; Zhu, Yan1; Sin, Sai-Weng2; Seng-Pan, U.2,3; Martins, Rui P.2; Maloberti, Franco4
2017-08
Source PublicationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN1549-8328
Volume64Issue:8Pages:1966-1976
Abstract

This paper proposes a 5-b 5-GS/s time-based flash ADC in 65-nm digital CMOS technology, which utilizes both rising and falling edges of the clock for sampling and quantization. A dual-edge-triggered scheme reduces the dynamic power consumption of a voltage-to-time converter and the clock buffers by half. We doubled both the reset and the available regeneration times by interleaving the time comparators. The ADC has a low input capacitance and the calibration circuit is included on-chip for suppressing various mismatches. The prototype running at 5 GS/s consumes 7.8 mW from a 1-V supply and achieves a signal-to-noise and distortion ratio of 26.19 dB at Nyquist. The resulting figure of merit is 94.6 fJ/conversion-step and the core area is only 0.004 mm(2).

KeywordAnalog-to-digital Converter (Adc) Flash Time-based Dual-edge-triggered
DOIhttp://doi.org/10.1109/TCSI.2017.2682268
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000406463900002
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
Fulltext Access
Citation statistics
Cited Times [WOS]:4   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorChan, Chi-Hang; Martins, Rui P.
Affiliation1.the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao 999078, China
2.the State Key Laboratory of Analog and Mixed-Signal VLSI and Department of ECE, University of Macau, Macao 999078, China
3.Synopsys Macau Ltd, Macao 999078, China
4.the University of Pavia, 27100 Pavia, Italy
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chan, Chi-Hang,Zhu, Yan,Sin, Sai-Weng,et al. A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2017,64(8):1966-1976.
APA Chan, Chi-Hang,Zhu, Yan,Sin, Sai-Weng,Seng-Pan, U.,Martins, Rui P.,&Maloberti, Franco.(2017).A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,64(8),1966-1976.
MLA Chan, Chi-Hang,et al."A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 64.8(2017):1966-1976.
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