Please use this identifier to cite or link to this item: http://repository.umac.mo/handle/10692/1589
Title: A 2.3 mw 10-bit 170 ms/s two-step binary-search assisted time-interleaved SAR ADC
Authors: Wong, Si Seng
Chio, U Fat
Zhu, Yan
Sin, Sai Weng (冼世榮)
U, Seng Pan (余成斌)
Martins, Rui Paulo Da Silva
Issue Date: Aug-2013
Publisher: IEEE
Citation: IEEE journal of solid-state circuits, Aug. 2013, v. 48, no. 8, p. 1783-1794
Abstract: This paper presents the architecture of a 10b 170 MS/s two-step binary-search assisted time-interleaved SAR ADC. The front-end stage of this ADC is built with a 5b binary-search ADC, which is shared by two time-interleaved 6b SAR ADCs in the second-stage. The design does not use any static component such as op-amp or preamplifier that causes large dissipation of static power. DAC settling speed and power are also relaxed thanks to this architecture. Besides, the process insensitive asynchronous logic further reduces the delay of SA loop rather than using worst case delay cells to compensate the process variation problem. The ADC was fabricated in 65 nm CMOS and achieves 54.6 dB SNDR at 170 MS/s with only 2.3 mW of power consumption, leading to a FoM of 30.8 fJ/conversion-step.
URI: http://hdl.handle.net/10692/1589
ISSN: 0018-9200
Keywords: SAR ADC
Binary-search ADC
Analog-to-digital converter (ADC)
Ttime-interleaved
Two-step ADC
Access: http://dx.doi.org/10.1109/JSSC.2013.2258832
Appears in Collections:ECE Journal Articles

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