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N-Bits Successive Approximation Register Analog-to-Digital Converting System
Yan Zhu1; Chi Hang Chan1; U Fat Chio1; Sai Weng Sin1; Seng Pan U1; Rui Paulo Da Silva Martins1; Franco Maloberti2
2013
Rights HolderUNIVERSITY OF MACAU
Date Available2013
CountryUnited States
Subtype发明专利
Abstract

The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising : an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

Application Date2011-06-01
Patent NumberUS8344931B2
Application NumberUS13150508
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Document TypePatent
专题INSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.UNIVERSITY OF MACAU
2.Torre d' Isola I
First Author AffilicationUniversity of Macau
推荐引用方式
GB/T 7714
Yan Zhu,Chi Hang Chan,U Fat Chio,et al. N-Bits Successive Approximation Register Analog-to-Digital Converting System. US8344931B2[P]. 2013-01-01.
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