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Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption
Sai-Weng Sin1; Li Ding1; Yan Zhu1; He-Gong Wei1; Chi-Hang Chan1; U-Fat Chio1; Seng-Pan U1; Rui Paulo da Silva Martins1; Franco Maloberti2
2013-04-23
Rights HolderUniversity of Macau
CountryUnited States
Subtype发明专利
Abstract

An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Application Date2011-09-14
Patent NumberUS8427355B2
Application NumberUS13232442
Fulltext Access
Document TypePatent
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.University of Macau
2.Torre d' Isola IT
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Sai-Weng Sin,Li Ding,Yan Zhu,et al. Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption. US8427355B2[P]. 2013-04-23.
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