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A 1.2-V 10-bit 60–360MS/s Time-Interleaved Pipelined ADC in 0.18μm CMOS with Minimized Supply Headroom
S.-W. Sin1; Seng-Pan U1,2; R.P. Martins1,3
2010-01
Source PublicationIET Circuits, Devices & Systems
ISSN1751-858X
Volume4Issue:1Pages:1-13
Abstract

A low-voltage 1.2-V, 10-bit, 60–360 MS/s six channels time-interleaved reset-opamp pipelined ADC is designed and implemented in a 0.18-mm CMOS (VTHN/VTHP ¼ 0.63 V/20.65 V for mid-supply floating switches). Without using on-chip high-voltage and low-VT options, the proposed ADC employs low-voltage resistivedemultiplexing techniques, low-voltage gain-and-offset compensation, feedback current biasing to reduce the sensitivity of the bias current over process variations and current-mode sub-ADCs with static current sharing for a low-voltage time-interleaved implementation. Speed options of 60– 360 MS/s are available with scalable power and they can be obtained by automatic selection of the number of time-interleaved channels. The chip measurement results show that the ADC exhibits a differential non-linearity (DNL)/integral non-linearity (INL) better than 0.9/1.2 LSB and a peak SNDR above 54 dB, for all speed options, while consuming 85 mW at 60 MS/s and 426 mW at 360 MS/s. The active die area is 13.2 mm2 .

DOIhttp://doi.org/10.1049/iet-cds.2008.0229
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000275012900001
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Cited Times [WOS]:7   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Corresponding AuthorS.-W. Sin
Affiliation1.Analog and Mixed Signal VLSI Laboratory, Faculty of Science and Technology, University of Macau, Macao, People’s Republic of China
2.Chipidea Microelectronics, Macao, People’s Republic of China
3.on leave from Instituto Superior Te´cnico/TU of Lisbon
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
S.-W. Sin,Seng-Pan U,R.P. Martins. A 1.2-V 10-bit 60–360MS/s Time-Interleaved Pipelined ADC in 0.18μm CMOS with Minimized Supply Headroom[J]. IET Circuits, Devices & Systems,2010,4(1):1-13.
APA S.-W. Sin,Seng-Pan U,&R.P. Martins.(2010).A 1.2-V 10-bit 60–360MS/s Time-Interleaved Pipelined ADC in 0.18μm CMOS with Minimized Supply Headroom.IET Circuits, Devices & Systems,4(1),1-13.
MLA S.-W. Sin,et al."A 1.2-V 10-bit 60–360MS/s Time-Interleaved Pipelined ADC in 0.18μm CMOS with Minimized Supply Headroom".IET Circuits, Devices & Systems 4.1(2010):1-13.
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