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16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur
Zunsong Yang1; Yong Chen1; Shiheng Yang1; Pui-In Mak1; Rui P. Martins1,2
2019-02
Conference Name2019 IEEE International Solid- State Circuits Conference - (ISSCC)
Source Publication2019 IEEE International Solid- State Circuits Conference - (ISSCC)
Conference Date17-21 Feb. 2019
Conference PlaceSan Francisco, CA, USA, USA
Abstract

Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at low power. Without noisy loop components, the injection-locked PLL in [1] using a GHz reference (REF=2.25 GHz) can effectively suppress the integrated jitter (86fsrms), resulting in a better jitter-power FoM (-247.2dB). Yet, high-frequency REF injection leads to large spur (-32dBc), entailing continuous frequency tracking to withstand the PVT variations. Also, at the system level, the GHz REF has to be generated on-chip (i.e., cascaded PLLs). The power overhead, e.g., additional 20mW in [2], and unwanted coupling between the two VCOs become inevitable. To this end, direct-synthesis mm-wave PLLs using a MHz REF are of higher interest, despite the challenge of a large division ratio (N). An example is a Type-II mm-wave PLL reported in [3] that achieves 115fsrms integrated jitter, but the involved divider, charge pump (CP), and VCO totally draw 31mW to suppress the in-band and out-of-band phase noise (PN).

DOI10.1109/ISSCC.2019.8662364
Indexed BySCI
Language英语
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Document TypeConference paper
CollectionFaculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.University of Macau, Macau, China
2.Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Zunsong Yang,Yong Chen,Shiheng Yang,et al. 16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur[C],2019.
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