Complex-Pole Load Offering Concurrent Image Rejection and Channel Selection | |
Zhicheng Lin; Pui-In Mak![]() ![]() | |
2014-04-17 | |
Rights Holder | University of Macau |
Date Available | 2015-10-22 |
Country | United States |
Subtype | 发明专利 |
Contribution Rank | 1 |
Abstract | A complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative IF (−IF) for channel selection and image rejection, offering image rejection and channel selection concurrently. |
Application Date | 2014-04-17 |
Patent Number | US20150303955A1 |
Language | 英语 |
Application Number | US14255094 |
Open (Notice) Number | US20150303955A1 |
Fulltext Access | |
Document Type | Patent |
Collection | Faculty of Science and Technology DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Affiliation | University of Macau |
First Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Zhicheng Lin,Pui-In Mak,Rui Paulo da Silva Martins. Complex-Pole Load Offering Concurrent Image Rejection and Channel Selection. US20150303955A1[P]. 2014-04-17. |
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