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Complex-Pole Load Offering Concurrent Image Rejection and Channel Selection
Zhicheng Lin; Pui-In Mak; Rui Paulo da Silva Martins
2014-04-17
Rights HolderUniversity of Macau
Date Available2015-10-22
CountryUnited States
Subtype发明专利
Contribution Rank1
Abstract

A complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative IF (−IF) for channel selection and image rejection, offering image rejection and channel selection concurrently.

Application Date2014-04-17
Patent NumberUS20150303955A1
Language英语
Application NumberUS14255094
Open (Notice) NumberUS20150303955A1
Fulltext Access
Document TypePatent
CollectionFaculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
AffiliationUniversity of Macau
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Zhicheng Lin,Pui-In Mak,Rui Paulo da Silva Martins. Complex-Pole Load Offering Concurrent Image Rejection and Channel Selection. US20150303955A1[P]. 2014-04-17.
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