This paper presents a 1-V 10b 40MS/s Pipelined ADC with an effective resolution bandwidth up to 66MHz. Two low-voltage circuit techniques are employed: 1) feedback current biasing - which ensures the accuracy of the current source biasing over the process variations without the use of cascode structure in low-voltage environment; 2) low-voltage current-mode sub-ADCs - which allows current-mirror sharing between the low-voltage comparators thus implying a reduction in static power consumption. The proposed ADC was implemented in 0.18um IP6M CMOS technology. Chip measurement results show that the DNL and INL are within 0.9 and 1.1 LSB, respectively. The ADC maintains the SNDR over 54.5dB and 51.5dB for input frequencies of 9.1MHz and 66MHz, respectively. The active die area is 2.2mm and the ADC consumes 40mW at 1-V supply.