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A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS
Sai-Weng Sin; Seng-Pan U; R.P.Martins
2009
Source Publication澳門機電工程專業協會(APEMEM)會刊
Abstract

This paper presents a 1-V 10b 40MS/s Pipelined ADC with an effective resolution bandwidth up to 66MHz. Two low-voltage circuit techniques are employed: 1) feedback current biasing - which ensures the accuracy of the current source biasing over the process variations without the use of cascode structure in low-voltage environment; 2) low-voltage current-mode sub-ADCs - which allows current-mirror sharing between the low-voltage comparators thus implying a reduction in static power consumption. The proposed ADC was implemented in 0.18um IP6M CMOS technology. Chip measurement results show that the DNL and INL are within 0.9 and 1.1 LSB, respectively. The ADC maintains the SNDR over 54.5dB and 51.5dB for input frequencies of 9.1MHz and 66MHz, respectively. The active die area is 2.2mm and the ADC consumes 40mW at 1-V supply.

KeywordIndex Terms-pipelined Adc Low-voltage Current-mode Comparator
Language英语
Fulltext Access
Document TypeJournal article
CollectionFaculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorSai-Weng Sin; Seng-Pan U; R.P.Martins
AffiliationAnalog and Mixed-Signal VLSI Laboratory, FST, University of Macau, Macao, China
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Sai-Weng Sin,Seng-Pan U,R.P.Martins. A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS[J]. 澳門機電工程專業協會(APEMEM)會刊,2009.
APA Sai-Weng Sin,Seng-Pan U,&R.P.Martins.(2009).A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS.澳門機電工程專業協會(APEMEM)會刊.
MLA Sai-Weng Sin,et al."A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS".澳門機電工程專業協會(APEMEM)會刊 (2009).
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