UM  > 科技學院  > 電機及電腦工程系
1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom
S.-W. Sin1; Seng-Pan U1,2; R.P. Martins1
2010-01
Source PublicationIET Circuits, Devices & Systems
ISSN1751-858X
Volume4Issue:1Pages:1-13
Abstract

A low-voltage 1.2-V, 10-bit, 60–360 MS/s six channels time-interleaved reset-opamp pipelined ADC is designed and implemented in a 0.18-mm CMOS (VTHN/VTHP ¼ 0.63 V/20.65 V for mid-supply floating switches). Without using on-chip high-voltage and low-VT options, the proposed ADC employs low-voltage resistivedemultiplexing techniques, low-voltage gain-and-offset compensation, feedback current biasing to reduce the sensitivity of the bias current over process variations and current-mode sub-ADCs with static current sharing for a low-voltage time-interleaved implementation. Speed options of 60– 360 MS/s are available with scalable power and they can be obtained by automatic selection of the number of time-interleaved channels. The chip measurement results show that the ADC exhibits a differential non-linearity (DNL)/integral non-linearity (INL) better than 0.9/1.2 LSB and a peak SNDR above 54 dB, for all speed options, while consuming 85 mW at 60 MS/s and 426 mW at 360 MS/s. The active die area is 13.2 mm

DOIhttp://doi.org/10.1049/iet-cds.2008.0229
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000275012900001
全文获取链接
引用统计
被引频次[WOS]:7   [WOS记录]     [WOS相关记录]
Document TypeJournal article
专题DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Corresponding AuthorS.-W. Sin
Affiliation1.Analog and Mixed Signal VLSI Laboratory, Faculty of Science and Technology, University of Macau, Macao, People’s Republic of China
2.Chipidea Microelectronics, Macao, People’s Republic of China1
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
推荐引用方式
GB/T 7714
S.-W. Sin,Seng-Pan U,R.P. Martins. 1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom[J]. IET Circuits, Devices & Systems,2010,4(1):1-13.
APA S.-W. Sin,Seng-Pan U,&R.P. Martins.(2010).1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom.IET Circuits, Devices & Systems,4(1),1-13.
MLA S.-W. Sin,et al."1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom".IET Circuits, Devices & Systems 4.1(2010):1-13.
个性服务
推荐该条目
保存到收藏夹
查看访问统计
导出为Endnote文件
Google Scholar
中相似的文章 Google Scholar
[S.-W. Sin]的文章
[Seng-Pan U]的文章
[R.P. Martins]的文章
Baidu academic
中相似的文章 Baidu academic
[S.-W. Sin]的文章
[Seng-Pan U]的文章
[R.P. Martins]的文章
Bing Scholar
中相似的文章 Bing Scholar
[S.-W. Sin]的文章
[Seng-Pan U]的文章
[R.P. Martins]的文章
相关权益政策
暂无数据
收藏/分享
所有评论 (0)
暂无评论
 

除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。