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Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering
U Seng Pan1; Martins Rui Paulo1; Epifanio da Franca Jose de Albuquerque2
Subtype
2006
PublisherSpringer US
Publication PlaceUS
Other Abstract
  • Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/​PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.
KeywordCmos Cmos Analog Integrated Circuit Filter Front-end Filtering Gain & Offset Compensation High-frequency Multirate Signal Processing Secs Switched-capacitor The Kluwer International Series In engIneerIng And Computer Timing-mismatch And Jitter Calculus Consumption Integrated Circuit
ISBN978-0-387-26121-8
DOIhttp://doi.org/10.1007/b136837
Is Part of SeriesThe Kluwer International Series in Engineering and Computer Science – Analog Circuits and Signal Processing ; The Kluwer International Series in Engineering and Computer Science – Analog Circuits and Signal Processing
Pages250
Language英语
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Document TypeBook
CollectionFaculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.University of Macau, Macau
2.Instituto Superior Técnico
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
U Seng Pan,Martins Rui Paulo,Epifanio da Franca Jose de Albuquerque. Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering[M]. US:Springer US,2006.
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